![]() ![]() ![]() CONFIRM : if index = 0 : if sync_flag : state. posedge, reset = reset_n ) def FSM (): if reset_n = ACTIVE_LOW : sof. sof - start-of-frame output bit state - FramerState output sync_flag - sync pattern found indication input clk - clock input reset_n - active low reset """ index = Signal ( intbv ( 0, min = 0, max = FRAME_SIZE )) # position in frame ( clk. The simulation produces the following outputįrom myhdl import block, always_seq, Signal, intbv, enum ACTIVE_LOW = 0 FRAME_SIZE = 8 t_state = enum ( 'SEARCH', 'CONFIRM', 'SYNC' ) def framer_ctrl ( sof, state, sync_flag, clk, reset_n ): """ Framing control FSM. posedge yield delay ( 1 ) print ( " %s %s " % ( int ( enable ), count )) return clockGen, stimulus, inc_1, monitor tb = testbench () tb. negedge raise StopSimulation () def monitor (): print ( "enable count" ) yield reset. next = min ( 1, randrange ( 3 )) yield clock. ![]() next = INACTIVE_HIGH for i in range ( 16 ): enable. ![]() randrange ACTIVE_LOW, INACTIVE_HIGH = 0, 1 def testbench (): m = 3 count = Signal ( modbv ( 0 )) enable = Signal ( bool ( 0 )) clock = Signal ( bool ( 0 )) reset = ResetSignal ( 0, active = 0, isasync = True ) inc_1 = inc ( count, enable, clock, reset ) HALF_PERIOD = delay ( 10 ) ( HALF_PERIOD ) def clockGen (): clock. ResetSignal, modbv, delay, StopSimulation from inc import inc random. Import random from myhdl import block, always, instance, Signal, \ ![]()
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